There doesn't seem to be much detail anywhere else either. All I was able to gather was that the memory dies are stacked (not new) but that the vias connecting the stack are angled instead of straight up and down and this is better because ... reasons?
«[T]he primary standout feature of this memory solution is the integration of a staggered interconnect topology that routes connections diagonally within the die stack rather than drilling straight down. According to Intel, the biggest benefit lies in ZAM's thermal capabilities.»
The connectors on the side indeed look like the letter Z. Maybe it disperses the stronger currents across the stack of the crystals, instead of concentrating.
I thought this was going to mean each stack was able to directly talk to the controller, since all stacks are resting on an interposer thing. But actually there is still a logic controller slice at the bottom of the stack, not at a right angle to the stack.
Instead of HBM microbumps between layers there is a more compact/dense TSV ("fusion bonded via-in-one") system. Intel once more showing their strong chiplet packing prowess! The claim is that thermals are still much better somehow, in spite of volumetric cell density increasing (from thinner layers). The demo has 8+1 dram+controller layers.
But will this go the way of a “non core” product like Optane (or modems for that matter?)
The article says nothing about the construction or special qualities of ZAM, as compared to HBM :(
There doesn't seem to be much detail anywhere else either. All I was able to gather was that the memory dies are stacked (not new) but that the vias connecting the stack are angled instead of straight up and down and this is better because ... reasons?
Indeed, what is it? The article doesn't say, only espouses the supposed benefits.
Looks like an evolution of HBM.
https://wccftech.com/intel-showcases-its-zam-memory-prototyp...
«[T]he primary standout feature of this memory solution is the integration of a staggered interconnect topology that routes connections diagonally within the die stack rather than drilling straight down. According to Intel, the biggest benefit lies in ZAM's thermal capabilities.»
The connectors on the side indeed look like the letter Z. Maybe it disperses the stronger currents across the stack of the crystals, instead of concentrating.
It’s crazy that we have stalled on the structure of the basic DRAM cell for decades now.
This wccf article also doesn't do a great job of describing, but the third slide it shows is very illustrative: rather than stack horizontally it stacks dram on its side. https://wccftech.com/intel-zam-memory-threatens-hbms-ai-thro...
I thought this was going to mean each stack was able to directly talk to the controller, since all stacks are resting on an interposer thing. But actually there is still a logic controller slice at the bottom of the stack, not at a right angle to the stack.
Instead of HBM microbumps between layers there is a more compact/dense TSV ("fusion bonded via-in-one") system. Intel once more showing their strong chiplet packing prowess! The claim is that thermals are still much better somehow, in spite of volumetric cell density increasing (from thinner layers). The demo has 8+1 dram+controller layers.