This was the research paper which introduced the abbreviation "VLIW" and contrasted it with the concept of RISC, which had been introduced a few years earlier (the term RISC had been coined in October 1980, but the concept was older than that, coming from the IBM 801 project, a few years earlier).
At that time, the easiest way to understand the difference between RISC and VLIW CPUs and earlier CPUs was to compare them with the microprogrammed CPUs of the seventies, which used either "vertical microprogramming" or "horizontal microprogramming".
RISC CPUs could be viewed as modified vertically microprogrammed CPUs and VLIW CPUs could be viewed as modified horizontally microprogrammed CPUs.
In both cases the modification consisted in replacing the read-only microprogram memory with a read-write cache memory and eliminating the decoder that converted complex instructions into simple vertical microinstructions or horizontal microinstructions.
Thus what was previously the simpler instruction set used in microprograms became the programmer-visible ISA.
The term "vertical" had been applied to microinstructions that executed one simple operation per clock cycle, while "horizontal" was applied to microinstructions that executed in parallel multiple simple operations per clock cycle. Horizontal microinstructions differed from vector instructions a.k.a. SIMD instructions, because for each concurrent operation it was possible to specify in the encoding distinct source and destination registers from those used by the concurrent operations.
A few years later after this VLIW paper, IBM coined the word "superscalar" which was applied to a CPU structure that was improved over VLIW by adding a dynamic scheduler for the concurrently executed operations, replacing their static scheduling done by the programmer or the compiler.
While the word "superscalar" was coined only in March 1987, the concept of using a dynamic scheduler to enable the out-of-order execution of multiple operations per clock cycle was much older, being described in an internal confidential document of IBM from 1966-02-23 (inventor: Lynn Conway).
That document was not known outside IBM for many years, but John Cocke, one of the 2 proponents of the superscalar CPUs had been a member of the IBM ACS team, so he must have read the original document about dynamic scheduling, 20 years before the concept was revived when the CMOS technology had become ready for it.
this gave me some old Itanic nostalgia just reading the foreword. There were some interesting discussions from 2024 regarding it and other people involved in VLIW designs
This was the research paper which introduced the abbreviation "VLIW" and contrasted it with the concept of RISC, which had been introduced a few years earlier (the term RISC had been coined in October 1980, but the concept was older than that, coming from the IBM 801 project, a few years earlier).
At that time, the easiest way to understand the difference between RISC and VLIW CPUs and earlier CPUs was to compare them with the microprogrammed CPUs of the seventies, which used either "vertical microprogramming" or "horizontal microprogramming".
RISC CPUs could be viewed as modified vertically microprogrammed CPUs and VLIW CPUs could be viewed as modified horizontally microprogrammed CPUs.
In both cases the modification consisted in replacing the read-only microprogram memory with a read-write cache memory and eliminating the decoder that converted complex instructions into simple vertical microinstructions or horizontal microinstructions.
Thus what was previously the simpler instruction set used in microprograms became the programmer-visible ISA.
The term "vertical" had been applied to microinstructions that executed one simple operation per clock cycle, while "horizontal" was applied to microinstructions that executed in parallel multiple simple operations per clock cycle. Horizontal microinstructions differed from vector instructions a.k.a. SIMD instructions, because for each concurrent operation it was possible to specify in the encoding distinct source and destination registers from those used by the concurrent operations.
A few years later after this VLIW paper, IBM coined the word "superscalar" which was applied to a CPU structure that was improved over VLIW by adding a dynamic scheduler for the concurrently executed operations, replacing their static scheduling done by the programmer or the compiler.
While the word "superscalar" was coined only in March 1987, the concept of using a dynamic scheduler to enable the out-of-order execution of multiple operations per clock cycle was much older, being described in an internal confidential document of IBM from 1966-02-23 (inventor: Lynn Conway).
That document was not known outside IBM for many years, but John Cocke, one of the 2 proponents of the superscalar CPUs had been a member of the IBM ACS team, so he must have read the original document about dynamic scheduling, 20 years before the concept was revived when the CMOS technology had become ready for it.
> Trace scheduling replaces block-by-block compaction of code with the compaction of long streams of code, possibly thousands of instructions long...
"Enormously Longinstruction Words" is very interesting, but for me the spotlight here is on "trace scheduling".
this gave me some old Itanic nostalgia just reading the foreword. There were some interesting discussions from 2024 regarding it and other people involved in VLIW designs
https://news.ycombinator.com/item?id=39097504